1. Field of the Invention
The present invention relates to a BGA semiconductor device and a manufacturing method thereof.
Priority is claimed on Japanese Patent Application No. 2008-136644, filed May 26, 2008, the content of which is incorporated herein by reference.
2. Description of Related Art
FIG. 13 is a schematic bottom view of a related ball grid array (BGA) semiconductor device.
As shown in FIG. 13, a related ball grid array (BGA) semiconductor device 101 includes a semiconductor chip 106 mounted on a wiring board 102, the semiconductor chip 106 usually being mounted such that each of its corners faces a corner of the wiring board 102. In other words, four sides of the semiconductor chip 106, which is substantially rectangular in plane view, are roughly parallel to the four sides of the wiring board 102, which is also substantially rectangular in plane view. The arrangement is such that, among a plurality of connection bumps 105 mounted in a matrix formation on the wiring board 102, connection bumps 105a at the corners are close to corners 102a of the wiring board 102. Thus, corners 106a of the semiconductor chip 106 roughly match the positions of the corner-portion connection bumps 105a among the plurality of connection bumps 105.
With such a structure, in packaging temperature cycle (TC) testing, stress generated by the difference in the linear expansion coefficients (α) of the wiring board 102 and the semiconductor chip 106, and by the difference in the linear expansion coefficients (α) of the semiconductor device 101 and a mount board, resulted in breakage of the connection bumps 105 made from solder balls and the like. The main reason for this is that connection bumps arranged close to the corners of the wiring board 102, and connection bumps arranged directly below the corners of the semiconductor chip 106, receive considerable stress. The reliability of the semiconductor device 101 deteriorates markedly as a result.
One countermeasure for preventing such connection bump breakage that has already been proposed is to increase the connection strength of the connection bumps by making only the connection bumps at the corners larger (Japanese Unexamined Patent Application, First Publication, No. 2001-210749). Another technique arranges the connection bumps concentrically around a center of the wiring board, thereby preventing damage caused by stress concentrating at a specific connection bump (Japanese Unexamined Patent Application, First Publication, No. Hei 09-162531).
While these techniques are effective against breakage of corner connection bumps among a plurality of connection bumps arranged in a matrix, they are not very practical. One reason is that, when the size and arrangement of the bumps are changed, the design of the wiring-board-side lands and the like must also be changed. Recently, the electronics industry is becoming increasingly specialized, and manufacturers of semiconductors and the like are choosing a single-business strategy, with a resultant trend towards fewer manufacturers who are jointly developing semiconductor chips and wiring boards. Name-brand manufacturers who do not have a semiconductor chip manufacturing section need to procure more versatile semiconductor chips from a plurality of semiconductor manufacturers, and, in regard to matters such as bump alignment, must standardize these with other companies wherever possible.
While the objective is different, techniques for tilting a semiconductor chip with respect to the wiring board, for example, are disclosed in Japanese Unexamined Patent Application, First Publications, No. 2006-73625, No. 2007-95964, and No. 2004-140079. However, when simply tilting the semiconductor chip with respect to the wiring board as in these related techniques, the size of the wiring board must be increased such that the semiconductor chip does not extrude from the wiring board due to the diagonal line being longer than one side of the semiconductor chip. When the size of the wiring board increases, the semiconductor device becomes bigger, and, when cutting the wiring board from a mother material of the wiring board, the number of products that can be taken from one wiring board mother material decreases, leading to a danger of higher cost.
When the size of the wiring board increases further, so does the amount of sealing resin for sealing the semiconductor chip on the wiring board, leading to an increase in stress arising from the difference between the linear expansion coefficients of the wiring board and the sealing resin, and a greater danger that the semiconductor device will be warped.
Further, in related techniques, there is a danger that the connection bumps will be disposed directly below the corners of a semiconductor chip that is tilted with respect to the wiring board, making the reliability of secondary mounting problematic. It is therefore impossible to realize a reliable and miniaturized semiconductor device.